This invention relates a CMOS frequency divide-by-2 analog circuit, and in particular to a frequency divider that is capable of operation at very low supply voltages and very high frequencies.
Previous designs of Source-Coupled-Logic-Based frequency dividers employ two D-flip-flops in master/slave configuration as shown in FIG. 1. The output signal of one of the D-flip-flops is fed back to the input of the other D-flip-flop, and vice versa. Each D-flip-flop is controlled by a pair of complementary clock signals (CLK and CLKBAR). The function of the frequency divider is to receive a CLK signal having a frequency as one of the input and to produce an output signal equal to substantially half of the CLK frequency.
A conventional high-speed frequency divider circuit is shown in FIG. 2. This circuit includes two identical D-flip-flop circuit sections. Each D-flip-flop needs a pair of complementary clock signals (CLK and CLKBAR) for proper operation. Each D-flip-flop includes a pair of PMOS transistors (Mp1, Mp2) for which their sources are connected to a DC voltage supply (Vdd). Clock signals are applied to these transistors"" gate terminals to control their resistance. Two pairs of NMOS transistor (Mn1, Mn2) and (Mn4, Mn5) are connected to the output nodes of each D-flip-flop. The transistor pair (Mn1, Mn2) is connected to a NMOS switch (Mn6), which is controlled to turn on and off by CLK signal. Another pair (Mn4, Mn5) is connected to a NMOS switch (Mn3) which is driven by CLKBAR signal for turning on and off. This circuit is operated as a dynamic-loading frequency divider. In particular, when the CLK signal is high (CLKBAR is low), the switch (Mn6) is turned on, and the (Mp1, Mp2) loading is operated in linear-region. In this case, NMOS pair (Mn4, Mn5) compares the amplitudes of the input signals from their input gate terminals and passes to the results to their output nodes. When the CLK signal is low (CLKBAR is high), the switches (Mn3) and (Mn6) are turned on and off respectively. The (Mp1, Mp2) loading is operated in the cutoff region. The NMOS pair (Mn1, Mn2) acts as positive feedback to latch the output node.
The main problem with such conventional designs is that the minimum required supply voltage (Vdd) is limited by the DC biasing requirements of the input gate terminals of the PMOS transistors (Mp1, Mp2) and the NMOS switches (Mn3, Mn6) at the same time.
In order to properly bias the PMOS transistors and the NMOS switches with low turn-on resistance, a minimum over-drive voltage (Voverdrive=VGSxe2x88x92VT) of 0.15V is usually required. As a result, the voltage supply for the conventional frequency divider (Vdd) has to be at least equal to |Vt(PMOS)|+Vt(NMOS)+0.3V. As an example, for a standard 0.35-mm CMOS process, Vt(PMOS)=0.8V, Vt(NMOS)=0.6V, the minimum supply voltage is equal to 1.7V.
As the supply voltage drops below 1 V, the frequency divider fails to function at high frequencies. Those familiar with the arts will readily understand the problem by considering a CMOS complementary inverter that operates at a 1-V supply. The inverter is only functional properly if it is driven by a rail-to-rail input clock signal. This is because the NMOS device can be turned on only with a clock signal (Vclk) xe2x80x9chighxe2x80x9d enough to overcome its threshold voltage (Vclk greater than Vtn) while the PMOS device can be turned on only with a clock signal (Vclk) xe2x80x9clowxe2x80x9d enough (Vclk less than Vddxe2x88x92|Vtp|). As a result, for a low supply voltage (Vdd less than Vtn+|Vtp|), there would exist a dead-zone region (Vtn greater than Vclk greater than Vddxe2x88x92|Vtp|) in which the inverter responds very slowly or even ceases to function. A similar problem occurs in the conventional frequency dividers at a low supply voltage.
In this invention, a frequency-divider circuit is proposed to operate at a very low voltage and a very high frequency, which is still not achievable with existing techniques. The invented frequency-divider circuit generates output signals having a frequency half of the frequency of the input (CLK) signal. The divider circuit consists of two identical D-flip-flops connected in a master/slave configuration. The outputs of each D-flip-flop are connected to the inputs of the other D-flip-flop. The first D-flip-flop is controlled by a single input (CLK) signal connecting to the PMOS loading and NMOS switching transistors. In parallel, the complementary input signal (CLKBAR) drives the PMOS loading and the NMOS switch of the second D-flip-flop. The present invention employs common-gate NMOS switches (rather than common-source NMOS switches as in prior arts) so that the DC biasing of the input signals (CLK and CLKBAR) can be optimized simultaneously for both the PMOS loadings and the NMOS. Those familiar with the field will understand that this novel technique helps enable the frequency-divider circuit to work at a minimum supply voltage of Vt(PMOS)+Voverdrive less than 1.0 V and to achieve multi-gigahertz frequency operation at the same time. Experimental results show that this new frequency-divider circuit can work at 1-V supply at a frequency up to 5.2 GHz in a standard 0.35-mm CMOS process. Moreover, simulated in a 0.18-mm CMOS process, the proposed divider can operate successfully at a frequency of more than 20 GHz with a 1-V supply. Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims.